This application is based upon and claims priority of Japanese Patent Application No. 2002-240540, filed on Aug. 21, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device where an element and wiring are connected via a silicide film, and a manufacturing method for the same. Particularly, the present invention relates to a semiconductor device including a transistor operating at low voltage and a transistor driven at high voltage like flush memory, and relates to a manufacturing method for the same.
2. Description of the Prior Art
A semiconductor device such as flush memory is composed of low voltage transistors operating at low voltage of 5 V or lower and high voltage transistors operating at high voltage of about 20 V, which are mixedly mounted.
FIG. 1 is a sectional view showing a connecting portion of the high voltage transistor and wiring in a conventional semiconductor device. With reference to the FIG. 1, a manufacturing method for the conventional semiconductor device will be described.
First, a trench is formed at a predetermined position of a semiconductor substrate 10. The trench is filled with an insulating material such as SiO2 (silicon oxide) to form an element isolation film 11. A surface of the semiconductor substrate 10 is then oxidized to form a gate insulation film (not shown). On the gate insulation film, a gate electrode 12 is formed in a predetermined pattern.
Thereafter, impurities are introduced into the surface of the semiconductor substrate 10 at comparatively low concentration using the gate electrode 12 as a mask to form a lightly doped drain (LDD) layers 13. The LDD layer 13 is formed on both sides of the gate electrode 12, but only one LDD layer 13 is shown in FIG. 1.
Over the entire upper surface of the semiconductor substrate 10, an insulation film such as SiO2 is formed. The insulation film is anisotropically etched to be left only on both sides of the gate electrode 12 as sidewalls 14.
Over the entire upper surface of the semiconductor substrate 10, an insulating material such as SiO2 is deposited to form an interlayer insulation film 15. The gate electrode 12, the LDD layer 13, the element isolation film 11 and the like are covered with this interlayer insulation film 15.
Subsequently, the interlayer insulation film 15 is selectively etched with photolithography to form a contact hole 15h reaching the LDD layer 13. Then, impurities are ion-implanted at high concentration into the surface of the semiconductor substrate 10 through the contact hole 15h to form a source/drain layer 13a. 
The contact hole 15h is then filled with an electrical conductor such as metal to form a contact plug 15a. Subsequently, a metallic film is formed on the interlayer insulation film 15 and then patterned by photolithography to form wiring 16.
In the semiconductor device manufactured in such a manner, a withstanding voltage of the transistor relates to a distance a between the source/drain layer 13a and the gate electrode 12. The longer the distance a is, the higher the withstanding voltage of the transistor is.
In recent years, miniaturization of the semiconductor devices tends to be further accelerated. Along with the miniaturization, the area of a contact portion between the wiring and any one of the gate electrode and the source/drain layer has been reduced. Accordingly, in order to further improve properties of the contact portion, a silicide film formed by a salicide process has become used.
FIG. 2 is a sectional view showing another example of the conventional semiconductor device. With reference to FIG. 2, a conventional method of manufacturing a semiconductor device including the salicide process will be described.
First, impurities are ion-implanted at high concentration into an element isolation region of the semiconductor substrate 20 to form an impurity region 21 for element isolation. A surface of the semiconductor substrate 20 in the element isolation region is oxidized to form an element isolation film 22.
The surface of the semiconductor substrate 20 in an element region is then oxidized to form a gate insulation film (not shown). On the gate insulation film, a gate electrode 23 is formed of polysilicon in a predetermined pattern. Subsequently, impurities are ion-implanted into the semiconductor substrate 20 at low concentration using the gate electrode 23 as a mask to form LDD layers 24. The LDD layers 24 are formed on both sides of the gate electrode 23.
Over the entire upper surface of the semiconductor substrate 20, an SiN (silicon nitride) film 25 to be a silicide block is then formed and patterned in a predetermined shape. Impurities are then ion-implanted at high concentration into each LDD layer 24 through an opening of the SiN film 25 to form a source/drain layer 24a. Over the entire upper surface of the semiconductor substrate 20, a metallic film such as cobalt or tungsten is formed and then heat-treated to form suicide films 26a and 26b on the surfaces of the gate electrode 23 and the source/drain layer 24a, respectively. Unreacted part of the metallic film is then removed by etching.
Subsequently, an insulation film such as SiO2 is deposited on the entire upper surface of the semiconductor substrate 20 to form an interlayer insulation film 27. In the interlayer insulation film 27, a contact hole 27h reaching the source/drain layer 24a is formed and filled with a conductive material to form a contact plug 27a. 
A metallic film is then formed on the interlayer insulation film 27 and patterned by photolithography to form wiring 28. In such a manner, the semiconductor device is completed.
However, the inventors consider that there is a problem shown below in the above described conventional method of manufacturing a semiconductor device.
In the semiconductor device shown in FIG. 2, the withstanding voltage of the transistor relates to a distance a between the gate electrode 23 and the source/drain layer 24a. On the other hand, when the contact hole 27h is formed in the interlayer insulation film 27 by photolithography, a margin b is necessary for mask alignment. The size of the silicide film 26b thereby needs to be larger than a size c of an end tip of the contact hole 27h. Accordingly, in the conventional method of manufacturing the semiconductor device, the transistor is increased in size by the margin b for mask alignment, that is, by the distance between an edge of the source/drain layer 24a and the contact plug 27a, thus limiting density improvement of the semiconductor device.
In the light of the above problem, an object of the present invention is to provide a semiconductor device including a silicide film on a gate electrode or a source/drain layer and allowing further density improvement compared with the conventional one, and a manufacturing method for the same.
The above subject is solved by a semiconductor device including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a low concentration impurity layer formed by introducing impurities at a low concentration into the semiconductor substrate on each side of the gate electrode; a first insulation film formed at least on the low concentration impurity layer; an opening provided in the first insulation film to expose part of the low concentration impurity layer; a source/drain layer formed by introducing impurities into the low concentration impurity layer at a position aligned with the opening at a concentration higher than that of the low concentration impurity layer; a silicide film formed by siliciding a surface of the source/drain layer; a second insulation film formed on the semiconductor substrate to cover the gate electrode and the first insulation film; a contact hole formed in a width larger than that of the opening at a position aligned with the opening in the second insulation film, the contact hole reaching the source/drain layer from a upper surface of the second insulation film via the opening; a contact plug formed by filling the contact hole with an electrical conductor; and wiring formed on the second insulation film and electrically connected to the silicide film via the contact plug.
In the present invention, the source/drain layer is formed at the position aligned with the opening of the first insulation film. In the present invention, the opening of the first insulation film (silicide block) is formed in a width smaller than that of the contact hole, and the silicide film on the source/drain layer and the contact plug are connected to each other via the opening. Accordingly, the distance between the gate electrode and the source/drain layer can be minimized, thus allowing density improvement of the semiconductor device while ensuring a required withstanding voltage.
The above subject can be solved by a manufacturing method for a semiconductor device including the steps of: forming a gate electrode on a semiconductor substrate; forming a low concentration impurity layer by introducing impurities into the semiconductor substrate at a low concentration using the gate electrode as a mask; forming a first insulation film on the semiconductor substrate and the gate electrode, and forming an opening exposing part of the low concentration impurity layer by patterning of the first insulation film; forming a source/drain layer by introducing impurities into the low concentration impurity layer through the opening at a concentration higher than that of the low concentration impurity layer; forming a silicide film by siliciding a surface of the source/drain layer inside the opening; forming a second insulation film over an entire upper surface of the semiconductor substrate; forming a contact hole exposing the silicide film by etching the second insulation film in a width larger than that of the opening of the first insulation film; forming a contact plug by filling the contact hole with an electrical conductor; and forming wiring on the second insulation film, the wiring being electrically connected to the silicide film via the contact plug.
In the present invention, the source/drain layer is formed by introducing impurities at a high concentration into the low concentration impurity layer through the opening of the first insulation film. Accordingly, the source/drain layer is approximately the same as the opening in size.
Subsequently, the second insulation film is formed on the semiconductor substrate, and the contact hole with a width larger than that of the opening of the first insulation film is formed by etching the second insulation film. At this time, if the etching is carried out under the condition where the etching rate of the second insulation film is kept higher than that of the first insulation film, the first insulation film is hardly etched. Accordingly, the space within the opening becomes as an end tip of the contact hole on the substrate side.
Consequently, the distance between the contact hole and the edge of the source/drain layer becomes almost zero, and the distance between the contact hole and the gate electrode is reduced compared with the conventional one. This enables the semiconductor device to be highly integrated.
Furthermore, the above described subject is solved by a semiconductor device including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a low concentration impurity layer formed by introducing impurities at a low concentration into the semiconductor substrate on each side of the gate electrode; a first insulation film formed on the low concentration impurity layer and the gate electrode; an opening provided in the first insulation film, the opening exposing part of the gate electrode; a silicide film formed by siliciding a surface of the gate electrode inside the opening; a second insulation film formed on the semiconductor substrate to cover the gate electrode and the first insulation film; a contact hole reaching the low concentration impurity layer from a upper surface of the second insulation film; a source/drain layer formed by introducing impurities into the low concentration impurity layer at a position aligned with the contact hole at a concentration higher than that of the low concentration impurity layer; a contact plug formed by filling the contact hole with an electrical conductor; and wiring formed on the second insulation film and electrically connected to the source/drain layer via the contact plug.
In the present invention, the silicide film is formed on the gate electrode using the first insulation film as a silicide block. The contact hole reaching the low concentration impurity layer from the upper surface of the second insulation film (interlayer insulation film) is formed. The source/drain layer is formed by introducing impurities at a high concentration into the low concentration impurity layer through the contact hole. Accordingly, the distance between the contact hole and the edge of the source/drain layer is almost zero, and density improvement of the semiconductor device is attained.
Still furthermore, the above described subject is solved by a manufacturing method for a semiconductor device, including the steps of: forming a gate electrode on a semiconductor substrate; forming a low concentration impurity layer by introducing impurities at a low concentration into the semiconductor substrate using the gate electrode as a mask; forming a first insulation film over an entire upper surface of the semiconductor substrate, and then forming an opening exposing part of the gate electrode by patterning the first insulation film; forming a silicide film by siliciding a surface of the gate electrode inside the opening; forming a second insulation film over an entire upper surface of the semiconductor substrate; forming a contact hole reaching the low concentration impurity layer from a upper surface of the second insulation film; forming a source/drain layer by introducing impurities into the low concentration impurity layer through the contact hole at a concentration higher than that of the low concentration impurity layer; forming a contact plug by filling the contact hole with an electrical conductor; and forming wiring on the second insulation film, the wiring being electrically connected to the source/drain layer via the contact plug.
In the present invention, the silicide film is formed on the gate electrode using the first insulation film as a silicide block. After the second insulation film (interlayer insulation film) is formed, the contact hole is formed, which reaches the low concentration impurity layer from the upper surface of the second insulation film. Thereafter, impurities are introduced at a high concentration into the low concentration impurity layer through the contact hole to form the source/drain layer. Accordingly, the distance between the contact hole and the edge of the source/drain layer becomes almost zero, and density improvement of the semiconductor is attained.